Most digital circuits operate on a master clock signal. In particular, the components of a computer circuit (e.g., central processing unit, floating point unit, memory, etc.) perform their individual operations in accordance with a common master clock signal.
A master clock signal is typically derived from a primary clock signal. Although a primary clock signal can be generated by any oscillating signal, the primary clock signal is typically generated from a crystal oscillator because a crystal oscillator generates a signal having a very stable frequency. Most crystal oscillators, however, do not have a well-controlled duty cycle. For this reason, the crystal oscillator is usually chosen to have a frequency twice that of the desired master clock signal frequency. The crystal oscillator signal is then fed into a divide-by-two circuit and then into a plurality of output buffers which output a plurality of master clock signals. Each master clock signal has a frequency one-half that of the crystal oscillator signal input frequency and has a controlled output duty cycle.
A typical clock distribution circuit 102 is shown in FIG. 1. A primary clock signal 101 is produced by a crystal oscillator 103. The clock distribution circuit 102 generates a master clock signal on each of N clock output lines 104. The clock distribution circuit 102 includes a divide-by-two circuit 105 and N buffer amplifiers 106. Each of the N clock output lines 104 carries a master clock signal to one or more of the components of computer circuitry, not shown.
For the computer system to work properly, clock pulses of the master clock signal must arrive simultaneously at each of the computer system components. In practice, however, there is always a small difference between the time a clock pulse arrives at one component and the time the same clock pulse arrives at another component within the computer system. This difference is called "clock skew." Computer systems generally have a certain tolerance to skew which diminishes as the clock frequency increases (as the time between clock transitions decreases).
Clock skew is a well-known difficulty occurring in clock distribution circuits. Clock skew is mostly caused by variation in integrated circuit process parameters which vary transistor switching times from transistor to transistor. Layout parasitics and packaging effects also contribute to clock skew.
Clock skew can be graphically illustrated by the timing diagram shown in FIG. 2. The graphed signals shown in FIG. 2 correspond to the circuit shown in FIG. 1. The primary clock signal 101 in FIG. 2 is an exemplary rising crystal oscillator signal provided to the input of the clock distribution circuit 102. The primary clock signal 101 has a transition 110 (e.g., a rising clock signal). Signals CLK 1, CLK 2, and CLK N all represent exemplary master clock signals on the corresponding outputs 104 of the clock distribution circuit 102 shown in FIG. 1. Of all of the master clock outputs, the first transition following the transition 110 in the primary clock signal 101 is a transition 112-1 in the master clock output signal CLK 1 (104-1). A transition 112-N in the signal CLK N (104-N), occurs after the transition 112-1 in the signal CLK 1 (104-1). A transition 112-2 in the signal CLK 2 (104-2) is the last transition of all of the clock output signals 104 to occur following the transition 110 in the primary clock signal 101. Thus, the time lapse between the transition 110 in the primary clock signal 101 and the transition 112-2 in the master clock signal CLK 2 is shown as a maximum time delay 115. Similarly, the time lapse between the transition 110 in the primary clock signal 101 and the transition 112-1 in the signal CLK 1 (104-1) is shown as a minimum time delay 113 among all of the clock outputs shown in FIG. 2. The transition 112-N in the master clock output signal CLK N (104-N) occurs between the transition 112-1 and the transition 112-2. The time delay between the transitions 112-1 and 112-2 in the master clock output signals 104 is called the clock skew 118.
A method for eliminating the skew between clock outputs is illustrated in FIG. 3. Variable delay elements 120 and 122 are added to the clock distribution circuit 102. After the components of the computer system have been assembled onto a printed-circuit board (PC board), the delay elements 120 and 122 are adjusted to add delay so that the skew between the master clock outputs 104 is nearly eliminated. Variable delay element 120, connected between the divide-by-two circuit 105 and the clock signal outputs, adds delay to all of the clock outputs. Variable delay elements 122 separately add delay to each of the master clock outputs 104.
This conventional adjustment procedure is very time consuming and is also prone to inaccuracy. Additionally, this method can consume significant area on the PC Board and it can consume substantial power. These and other factors contribute to increase the cost and inefficiency of utilizing such a procedure.